Verification Is Not Generation: Intent, Evidence, and Sign-off in the Age of AI
Every major advance in electronic design automation has not eliminated the role of the engineer—it has altered it. AI is proving to be no different.
Dr. Mo Fadiheh, Head of Research & Development, LUBIS EDA
Every major advance in electronic design automation has not eliminated the role of the engineer—it has altered it. AI is proving to be no different. What began as a research curiosity is now an engineering reality: large language models generate RTL, draft assertions, and assist with increasingly sophisticated verification tasks. The result is a tempting misconception that verification itself can be delegated to AI. Formal verification derives its value not from the volume of generated properties, but from the correctness of their underlying intent, the rigor of their interpretation, and the discipline of a proven verification process. AI will undoubtedly become a powerful accelerator for formal verification, but only when embedded within a systematic, human-guided methodology that preserves traceability, accountability, and, ultimately, sign-off confidence.
Modern verification failure is rarely caused by a shortage of code. A robust LLM can generate plausible SystemVerilog Assertions at scale, infer protocol behavior, propose corner cases, and translate specifications into checkable properties. What it cannot do—especially without expert oversight—is determine whether the specification is complete, whether a property captures the intended architectural guarantee, whether an assumption has over-constrained the environment, or whether a proof result has any meaningful bearing on silicon risk.
Consider an AI-assisted team developing a security-critical RISC-V subsystem. AI-generated RTL may accelerate repetitive implementation work, while the same models generate assertions for privilege checks, fault handling, cache coherence, and debug access. At first glance, this looks like verification progress. In practice, it may only be property-shaped code.
The hard work begins where generation ends. Verification is not the generation of properties; it is the disciplined construction of a defensible engineering argument that a design satisfies its intended behavior. Are the properties derived from a coherent threat model and architectural intent? Do they compose across privilege modes, exception paths, reset states, and microarchitectural optimizations? Are proof boundaries justified, or merely convenient? Have abstractions preserved the behavior that matters? Are covers, assumes, assertions, bindings, waivers, and convergence evidence managed as part of a controlled sign-off argument?
Methodology is the differentiator. Formal verification has always depended on experienced engineers: not merely to write properties, but to structure a comprehensive verification effort. A disciplined methodology decomposes large projects into well-defined tasks with clear ownership and review criteria. AI can automate many of those tasks, but responsibility for validating intent, interpreting results, and accepting evidence remains with the human engineer. Rather than reviewing a monolithic body of generated code, experts evaluate each verification objective independently, building confidence incrementally. The intentionality of the process is what allows a verification team to attain sign-off confidence.
AI will almost certainly improve the economics of formal verification by accelerating scaffolding, proposing property candidates, and reducing repetitive work. As verification collateral becomes easier to generate, however, the engineering challenge shifts from creation to governance. That is precisely why we at LUBIS EDA have built our business around a structured, repeatable verification methodology: one that decomposes complex verification efforts into discrete, reviewable tasks; maintains traceability from specification to sign-off; and enables human experts to evaluate evidence incrementally and scrupulously. Within such a framework, AI becomes another engineering tool, not a replacement for sound judgment. Ultimately, whether SystemVerilog originates from an engineer or a language model is secondary—what determines sign-off quality is the rigor of the process that transforms individual verification results into defensible engineering evidence.
Dr. Mo Fadiheh is Head of Research & Development at LUBIS EDA, where he leads the advancement of next-generation formal verification technologies. Mo’s work focuses on formal verification methodology, verification automation, and the scrupulous application of AI to create more scalable, trustworthy, and predictable verification flows.
LinkedIn: LUBIS EDA
LinkedIn: Mo Fadiheh
